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2006

A dynamically reconfigurable cache for multithreaded processors

8 years 8 months ago
A dynamically reconfigurable cache for multithreaded processors
Chip multi-processors (CMP) are rapidly emerging as an important design paradigm for both high performance and embedded processors. These machines provide an important performance alternative to increasing the clock frequency. In spite of the increase in potential performance, several issues related to resource sharing on the chip can negatively impact the performance of embedded applications. In particular, the shared on-chip caches make each job's memory access times dependent on the behavior of the other jobs sharing the cache. If not adequately managed, this can lead to problems in meeting hard real-time scheduling constraints. This work explores adaptable caching strategies which balance the resource demands of each application and in turn lead to improvements in throughput for the collective workload. Experimental results demonstrate speedups of up to
Alex Settle, Dan Connors, Enric Gibert, Antonio Go
Added 13 Dec 2010
Updated 13 Dec 2010
Type Journal
Year 2006
Where JEC
Authors Alex Settle, Dan Connors, Enric Gibert, Antonio González
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