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ICCD
2007
IEEE

Limits on voltage scaling for caches utilizing fault tolerant techniques

9 years 3 months ago
Limits on voltage scaling for caches utilizing fault tolerant techniques
This paper proposes a new low power cache architecture that utilizes fault tolerance to allow aggressively reduced voltage levels. The fault tolerant overhead circuits consume little energy, but enable the system to operate correctly and boost the system performance to close to defect free operation. Overall, power savings of over 40% are reported on standard benchmarks.
Mohammad A. Makhzan, Amin Khajeh Djahromi, Ahmed M
Added 15 Mar 2010
Updated 15 Mar 2010
Type Conference
Year 2007
Where ICCD
Authors Mohammad A. Makhzan, Amin Khajeh Djahromi, Ahmed M. Eltawil, Fadi J. Kurdahi
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