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2010
IEEE

Evaluating Bufferless Flow Control for On-chip Networks

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Evaluating Bufferless Flow Control for On-chip Networks
—With the emergence of on-chip networks, the power consumed by router buffers has become a primary concern. Bufferless flow control addresses this issue by removing router buffers, and handles contention by dropping or deflecting flits. This work compares virtual-channel (buffered) and deflection (packet-switched bufferless) flow control. Our evaluation includes optimizations for both schemes: buffered networks use custom SRAM-based buffers and empty buffer bypassing for energy efficiency, while bufferless networks feature a novel routing scheme that reduces average latency by 5%. Results show that unless process constraints lead to excessively costly buffers, the performance, cost and increased complexity of deflection flow control outweigh its potential gains:
George Michelogiannakis, Daniel Sanchez, William J
Added 29 Jan 2011
Updated 29 Jan 2011
Type Journal
Year 2010
Where NOCS
Authors George Michelogiannakis, Daniel Sanchez, William J. Dally, Christos Kozyrakis
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