Exact sat-based toffoli network synthesis

Compact realizations of reversible logic functions are of interest in the design of quantum computers. Such reversible functions are realized as a cascade of Toffoli gates. In this paper, we present the first exact synthesis algorithm for reversible functions using generalized Toffoli gates. Our iterative algorithm formulates the synthesis problem with d Toffoli gates as a sequence of Boolean Satisfiability (SAT) instances. Such an instance is satisfiable iff there exists a network representation with d gates. Thus, we can guarantee minimality. In addition to fully specified reversible functions, the algorithm can be applied to incompletely specified functions. For a set of benchmarks experimental results are given. Categories and Subject Descriptors B6.3 [Design Aids]: Automatic synthesis General Terms Design, Theory Keywords Reversible Logic, Quantum Circuits, Synthesis, Minimization, Boolean Satisfiability

• Type: Conference
• Year: 2007
• Where: GLVLSI
• Authors: Daniel Große, Xiaobo Chen, Gerhard W. Dueck, Rolf Drechsler
• Keywords: GLVLSI 2007, Reversible Functions, Reversible Logic, Toffoli Gates, VLSI