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2002

Finite Field Multiplier Using Redundant Representation

10 years 11 months ago
Finite Field Multiplier Using Redundant Representation
This article presents simple and highly regular architectures for finite field multipliers using a redundant representation. The basic idea is to embed a finite field into a cyclotomic ring which has a basis with the elegant multiplicative structure of a cyclic group. One important feature of our architectures is that they provide area-time trade-offs which enable us to implement the multipliers in a partial-parallel/hybrid fashion. This hybrid architecture has great significance in its VLSI implementation in very large fields. The squaring operation using the redundant representation is simply a permutation of the coordinates. It is shown that when there is an optimal normal basis, the proposed bit-serial and hybrid multiplier architectures have very low space complexity. Constant multiplication is also considered and is shown to have advantage in using the redundant representation.
Huapeng Wu, M. Anwarul Hasan, Ian F. Blake, Shuhon
Added 23 Dec 2010
Updated 23 Dec 2010
Type Journal
Year 2002
Where TC
Authors Huapeng Wu, M. Anwarul Hasan, Ian F. Blake, Shuhong Gao
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