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2008

A New Finite-Field Multiplier Using Redundant Representation

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A New Finite-Field Multiplier Using Redundant Representation
A novel serial-in parallel-out finite field multiplier using redundant representation is proposed. It is shown that the proposed architecture has either a significantly lower complexity and comparable critical path delay or a significantly smaller critical path delay and comparable complexity in comparison to the previously proposed architectures using the same representation. For the class of fields where there exists a type I optimal normal basis, the proposed multiplier compares favorably to the normal basis multipliers. A digit-level version for the new multiplier is also presented in this paper.
Ashkan Hosseinzadeh Namin, Huapeng Wu, Majid Ahmad
Added 15 Dec 2010
Updated 15 Dec 2010
Type Journal
Year 2008
Where TC
Authors Ashkan Hosseinzadeh Namin, Huapeng Wu, Majid Ahmadi
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