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DAC
2005
ACM

Full-chip analysis of leakage power under process variations, including spatial correlations

10 years 11 months ago
Full-chip analysis of leakage power under process variations, including spatial correlations
In this paper, we present a method for analyzing the leakage current, and hence the leakage power, of a circuit under process parameter variations that can include spatial correlations due to intra-chip variation. A lognormal distribution is used to approximate the leakage current of each gate and the total chip leakage is determined by summing up the lognormals. In this work, Both subthreshold leakage and gate tunneling leakage are considered. The proposed method is shown to be effective in predicting the CDF/PDF of the total chip leakage. The average errors for mean and sigma values are ? ?? and ??. Categories and Subject Descriptors B.8.2 [Hardware]: Performance and Reliability--Performance Analysis and Design Aids General Terms Algorithm, Design, Performance, Reliability
Hongliang Chang, Sachin S. Sapatnekar
Added 13 Nov 2009
Updated 13 Nov 2009
Type Conference
Year 2005
Where DAC
Authors Hongliang Chang, Sachin S. Sapatnekar
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