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2009
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On the Generation of Functional Test Programs for the Cache Replacement Logic

9 years 3 months ago
On the Generation of Functional Test Programs for the Cache Replacement Logic
Caches are crucial components in modern processors (both stand-alone or integrated into SoCs) and their test is a challenging task, especially when addressing complex and high-frequency devices. While the test of the memory array within the cache is usually accomplished resorting to BIST circuitry implementing March test inspired solutions, testing the cache controller logic poses some specific issues, mainly stemming from its limited accessibility. One possible solution consists in letting the processor execute suitable test programs, allowing the detection of possible faults by looking at the results they produce. In this paper we face the issue of generating suitable programs for testing the replacement logic in setassociative caches that implement a deterministic replacement policy. A test program generation approach based on modeling the replacement mechanism as a Finite State Machine (FSM) is proposed. Experimental results with a cache implementing a LRU policy are provided to a...
Wilson J. Perez, Danilo Ravotto, Edgar E. Sá
Added 09 Jul 2010
Updated 09 Jul 2010
Type Conference
Year 2009
Where ATS
Authors Wilson J. Perez, Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda, Alberto Paolo Tonda
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