Sciweavers

Share
ATS
2009
IEEE
92views Hardware» more  ATS 2009»
8 years 9 months ago
M-IVC: Using Multiple Input Vectors to Minimize Aging-Induced Delay
Negative bias temperature instability (NBTI) has been a significant reliability concern in current digital circuit design due to its effect of increasing the path delay with time a...
Song Jin, Yinhe Han, Lei Zhang 0008, Huawei Li, Xi...
ATS
2009
IEEE
92views Hardware» more  ATS 2009»
9 years 4 months ago
New Class of Tests for Open Faults with Considering Adjacent Lines
Hiroshi Takahashi, Yoshinobu Higami, Yuzo Takamats...
ATS
2009
IEEE
127views Hardware» more  ATS 2009»
9 years 4 months ago
On the Generation of Functional Test Programs for the Cache Replacement Logic
Caches are crucial components in modern processors (both stand-alone or integrated into SoCs) and their test is a challenging task, especially when addressing complex and high-fre...
Wilson J. Perez, Danilo Ravotto, Edgar E. Sá...
ATS
2009
IEEE
162views Hardware» more  ATS 2009»
9 years 6 months ago
Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial Coefficients
—A method of testing for parametric faults of analog circuits based on a polynomial representation of fault-free function of the circuit is presented. The response of the circuit...
Suraj Sindia, Virendra Singh, Vishwani D. Agrawal
ATS
2009
IEEE
135views Hardware» more  ATS 2009»
9 years 6 months ago
On Scan Chain Diagnosis for Intermittent Faults
Diagnosis is increasingly important, not only for individual analysis of failing ICs, but also for high-volume test response analysis which enables yield and test improvement. Sca...
Dan Adolfsson, Joanna Siew, Erik Jan Marinissen, E...
ATS
2009
IEEE
132views Hardware» more  ATS 2009»
9 years 6 months ago
On Improving Diagnostic Test Generation for Scan Chain Failures
In this paper, we present test generation procedures to improve scan chain failure diagnosis. The proposed test generation procedures improve diagnostic resolution by using multi-...
Xun Tang, Ruifeng Guo, Wu-Tung Cheng, Sudhakar M. ...
ATS
2009
IEEE
185views Hardware» more  ATS 2009»
9 years 6 months ago
Customized Algorithms for High Performance Memory Test in Advanced Technology Node
Embedded memory quality is critical to overall chip quality. New defect mechanisms that occur at advanced process nodes (65nm and below) are often more pronounced in memories due ...
Shomo Chen, Ning Huang, Ting-Pu Tai, Actel Niu
ATS
2009
IEEE
126views Hardware» more  ATS 2009»
9 years 6 months ago
Scan Chain Diagnosis by Adaptive Signal Profiling with Manufacturing ATPG Patterns
—In the past, software based scan chain defect diagnosis can be roughly classified into two categories (1) model-based algorithms, and (2) data-driven algorithms. In this paper w...
Yu Huang, Wu-Tung Cheng, Ruifeng Guo, Ting-Pu Tai,...
ATS
2009
IEEE
142views Hardware» more  ATS 2009»
9 years 6 months ago
Speeding up SAT-Based ATPG Using Dynamic Clause Activation
Abstract—SAT-based ATPG turned out to be a robust alternative to classical structural ATPG algorithms such as FAN. The number of unclassified faults can be significantly reduce...
Stephan Eggersglüß, Daniel Tille, Rolf ...
ATS
2009
IEEE
119views Hardware» more  ATS 2009»
9 years 6 months ago
Fault Diagnosis Using Test Primitives in Random Access Memories
As diagnostic testing for memory devices increasingly gains in importance, companies are looking for flexible, cost effective methods to perform diagnostics on their failing devi...
Zaid Al-Ars, Said Hamdioui
books