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2006
ACM

Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration

9 years 6 months ago
Generation of yield-aware Pareto surfaces for hierarchical circuit design space exploration
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based global optimization algorithm to generate the nominal pareto front efficiently using a simulator-in-a-loop approach. The solutions on this pareto front combined with efficient Monte Carlo approximation ideas are then used to compute the yield-aware pareto fronts. We show experimental results for both the nominal and yield-aware pareto fronts for power and phase noise for a voltage controlled oscillator (VCO) circuit. The presented methodology computes yield-aware pareto fronts in approximately 5-6 times the time required for a single circuit synthesis run and is thus practically efficient. We also show applications of yield-aware paretos to find the optimal VCO circuit to meet the system level specifications of a phase locked loop. Categories and Subject Descriptors B.7.2 [Integrated Circuits]: Design Aids Ge...
Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Ruten
Added 13 Nov 2009
Updated 13 Nov 2009
Type Conference
Year 2006
Where DAC
Authors Saurabh K. Tiwary, Pragati K. Tiwary, Rob A. Rutenbar
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