4 search results - page 1 / 1 » Generation of yield-aware Pareto surfaces for hierarchical c... |
DAC
2006
ACM
14 years 5 months ago
2006
ACM
Pareto surfaces in the performance space determine the range of feasible performance values for a circuit topology in a given technology. We present a non-dominated sorting based ...
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
This paper presents an exploration algorithm which examines execution time and energy consumption of a given application, while considering a parameterized memory architecture. Th...
DAC
2003
ACM
13 years 9 months ago
2003
ACM
We present a new technique to examine the trade-off regions of a circuit where its competing performances become “simultaneously optimal”, i.e. Pareto optimal. It is based on ...
DAC
1995
ACM
13 years 8 months ago
1995
ACM
Abstract— Many asynchronous designs are naturally specified and implemented hierarchically as an interconnection of separate asynchronous modules that operate concurrently and c...