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ASPDAC
2009
ACM
133views Hardware» more  ASPDAC 2009»
9 years 11 days ago
A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor
Performance evaluation is a serious challenge in designing or optimizing reconfigurable instruction set processors. The conventional approaches based on synthesis and simulations a...
Farhad Mehdipour, Hamid Noori, Bahman Javadi, Hiro...
GLVLSI
2007
IEEE
162views VLSI» more  GLVLSI 2007»
9 years 3 months ago
Utilizing custom registers in application-specific instruction set processors for register spills elimination
Application-specific instruction set processor (ASIP) has become an important design choice for embedded systems. It can achieve both high flexibility offered by the base processo...
Hai Lin, Yunsi Fei
DAC
1992
ACM
9 years 3 months ago
High Level Synthesis of Pipelined Instruction Set Processors and Back-End Compilers
Designing instruction set processors and constructing their compilers are mutually dependent tasks. Piper is a high level synthesis tool of ADAS which controls the hardware-softwa...
Ing-Jer Huang, Alvin M. Despain
DAC
1996
ACM
9 years 3 months ago
A Hardware/Software Partitioning Algorithm for Designing Pipelined ASIPs with Least Gate Counts
Abstract -- This paper introduces a new HW/SW partitioning algorithm used in automating the instruction set processor design for pipelined ASIP (Application Specific Integrated Pro...
Nguyen-Ngoc Bình, Masaharu Imai, Akichika S...
ASPDAC
2006
ACM
125views Hardware» more  ASPDAC 2006»
9 years 5 months ago
ASIP approach for implementation of H.264/AVC
- This paper presents an Application-Specific Instruction Set Processor (ASIP) approach for implementation of H.264/AVC. The proposed ASIP has special instructions for intra predic...
Sung Dae Kim, Jeong Hoo Lee, Chung Jin Hyun, Myung...
DATE
2007
IEEE
107views Hardware» more  DATE 2007»
9 years 5 months ago
Development of an ASIP enabling flows in ethernet access using a retargetable compilation flow
In this paper we research an FPGA based Application Specific Instruction Set Processor (ASIP) tailored to the needs of a flow aware Ethernet access node using a retargetable com...
K. Van Renterghem, P. Demuytere, Dieter Verhulst, ...
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