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ICCAD
2009
IEEE
123views Hardware» more  ICCAD 2009»
8 years 6 months ago
Multi-level clustering for clock skew optimization
Clock skew scheduling has been effectively used to reduce the clock period of sequential circuits. However, this technique may become impractical if a different skew must be appli...
Jonas Casanova, Jordi Cortadella
WICON
2010
8 years 6 months ago
Toward Clock Skew based Wireless Sensor Node Services
Clock skew is defined as the rate of deviation of a device clock from the true time. The frequency of a device's clock actually depends on its environment, such as the tempera...
Md. Borhan Uddin, Claude Castelluccia
SENSYS
2010
ACM
8 years 6 months ago
A case against routing-integrated time synchronization
To achieve more accurate global time synchronization, this paper argues for decoupling the clock distribution network from the routing tree in a multihop wireless network. We find...
Thomas Schmid, Zainul Charbiwala, Zafeiria Anagnos...
ICCAD
2010
IEEE
166views Hardware» more  ICCAD 2010»
8 years 6 months ago
Low-power clock trees for CPUs
Clock networks contribute a significant fraction of dynamic power and can be a limiting factor in high-performance CPUs and SoCs. The need for multi-objective optimization over a l...
Dongjin Lee, Myung-Chul Kim, Igor L. Markov
ICCAD
2010
IEEE
141views Hardware» more  ICCAD 2010»
8 years 6 months ago
Local clock skew minimization using blockage-aware mixed tree-mesh clock network
Clock network construction is one key problem in high performance VLSI design. Reducing the clock skew variation is one of the most important objectives during clock network synthe...
Linfu Xiao, Zigang Xiao, Zaichen Qian, Yan Jiang, ...
DAC
2010
ACM
8 years 6 months ago
Non-uniform clock mesh optimization with linear programming buffer insertion
Clock meshes are extremely effective at filtering clock skew from environmental and process variations. For this reason, clock meshes are used in most high performance designs. Ho...
Matthew R. Guthaus, Gustavo Wilke, Ricardo Reis
ASPDAC
2010
ACM
161views Hardware» more  ASPDAC 2010»
8 years 6 months ago
A dual-MST approach for clock network synthesis
Abstract--In nanometer-scale VLSI physical design, clock network becomes a major concern on determining the total performance of digital circuit. Clock skew and PVT (Process, Volta...
Jingwei Lu, Wing-Kai Chow, Chiu-Wing Sham, Evangel...
TMC
2010
179views more  TMC 2010»
8 years 6 months ago
On Fast and Accurate Detection of Unauthorized Wireless Access Points Using Clock Skews
We explore the use of clock skew of a wireless local area network access point (AP) as its fingerprint to detect unauthorized APs quickly and accurately. The main goal behind usi...
Suman Jana, Sneha Kumar Kasera
TCAD
2002
91views more  TCAD 2002»
8 years 8 months ago
Retiming and clock scheduling for digital circuit optimization
Abstract--This paper investigates the application of simultaneous retiming and clock scheduling for optimizing synchronous circuits under setup and hold constraints. Two optimizati...
Xun Liu, Marios C. Papaefthymiou, Eby G. Friedman
SIGMETRICS
2002
ACM
129views Hardware» more  SIGMETRICS 2002»
8 years 8 months ago
PC based precision timing without GPS
A highly accurate monitoring solution for active network measurement is provided without the need for GPS, based on an alternative software clock for PC's running Unix. With ...
Attila Pásztor, Darryl Veitch
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