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2008
IEEE

Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures

8 years 10 months ago
Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures
With the shift towards deep sub-micron (DSM) technologies, the increase in leakage power and the adoption of poweraware design methodologies have resulted in potentially significant variations in power consumption under different process, voltage and temperature (PVT) corners. In this paper, we first investigate the impact of PVT corners on power consumption at the System-on-Chip (SoC) level, especially for the on-chip communication infrastructure. Given a target technology library, we then show how it is possible to “scale d abstract the PVT variability at the system level, allowing characterization of the PVT-aware design space early in the design flow. We conducted several experiments to estimate power for PVT corner cases, at the gate-level, as well as at the higher system-level. Our preliminary results are very interesting and indicate that: (i) there are significant variations in power consumption across PVT corners, and (ii) the PVT-aware power estimation problem may be amena...
Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi,
Added 01 Jun 2010
Updated 01 Jun 2010
Type Conference
Year 2008
Where VLSID
Authors Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil Dutt
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