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ICCAD
1995
IEEE

LOT: logic optimization with testability-new transformations using recursive learning

10 years 1 months ago
LOT: logic optimization with testability-new transformations using recursive learning
: A new approach to optimize multi-level logic circuits is introduced. Given a multi-level circuit, the synthesis method optimizes its area, simultaneously enhancing its random pattern testability. The method is based on structural transformations at the gate level. New transformations involving EX-OR gates derived based on indirect implications by Recursive Learning have been introduced in the synthesis of multi-level circuits. This method is augmented with transformations that speci cally enhance randompattern testability while reducing the area. Testability enhancement is an integral part of our synthesis methodology. Experimental results show that the proposed methodology can not only realize lower area, but also achieves better testability compared to testability enhancement synthesis tools such as tstfx. Speci cally for ISCAS-85 benchmark circuits, it was observed that EX-OR gate-based transformations can yield smaller circuits compared to state-of-the-art logic optimization tool...
Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang K
Added 26 Aug 2010
Updated 26 Aug 2010
Type Conference
Year 1995
Where ICCAD
Authors Mitrajit Chatterjee, Dhiraj K. Pradhan, Wolfgang Kunz
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