ICCAD
1995
IEEE
13 years 8 months ago
1995
IEEE
: A new approach to optimize multi-level logic circuits is introduced. Given a multi-level circuit, the synthesis method optimizes its area, simultaneously enhancing its random pat...
DAC
2009
ACM
14 years 6 months ago
2009
ACM
This paper describes a function-based timing-driven optimization technique for the synthesis of multi-level logic circuits. Motivated by the principles of parallel prefix computat...