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ISCAS
2007
IEEE

Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers

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Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift Registers
—This paper shows that, for a given power budget, a shift register based multi-phase clock generator (MPCG) generates less jitter than a delay-locked loop (DLL) equivalent when both are realized with current mode logic (CML) circuits and white noise is assumed. This is due to the factor that the shift register MPCG has no jitter accumulation from one clock phase to the other as in the DLL based MPCG. For N-phase clock generation, the shift register MPCG needs a reference clock with N times higher frequency and thus requires a VCO with higher frequency than the DLL counterpart. However, we can show that this does not lead to additional power consumption.
Xiang Gao, Eric A. M. Klumperink, Bram Nauta
Added 04 Jun 2010
Updated 04 Jun 2010
Type Conference
Year 2007
Where ISCAS
Authors Xiang Gao, Eric A. M. Klumperink, Bram Nauta
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