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2007
IEEE

Mechanisms for bounding vulnerabilities of processor structures

12 years 4 months ago
Mechanisms for bounding vulnerabilities of processor structures
Concern for the increasing susceptibility of processor structures to transient errors has led to several recent research efforts that propose architectural techniques to enhance reliability. However, real systems are typically required to satisfy hard reliability budgets, and barring expensive full-redundancy approaches, none of the proposed solutions treat any reliability budgets or bounds as hard constraints. Meeting vulnerability bounds requires monitoring vulnerabilities of processor structures and taking appropriate actions whenever these bounds are violated. This mandates treating reliability as a first-order microarchitecture design constraint, while optimizing performance as long as reliability requirements are satisfied. This paper makes three key contributions towards this goal: (i) we present a simple infrastructure to monitor and provide upper bounds on the vulnerabilities of key processor structures at cyclelevel fidelity; (ii) we propose two distinct control mechanism...
Niranjan Soundararajan, Angshuman Parashar, Anand
Added 03 Jun 2010
Updated 03 Jun 2010
Type Conference
Year 2007
Where ISCA
Authors Niranjan Soundararajan, Angshuman Parashar, Anand Sivasubramaniam
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