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2007
IEEE

Model Based Test Generation for Microprocessor Architecture Validation

10 years 7 months ago
Model Based Test Generation for Microprocessor Architecture Validation
Functional validation of microprocessors is growing in complexity in current and future microprocessors. Traditionally, the different components (or validation collaterals) used in simulation based validation, like simulators generators, to validate the system, architecture, microcode, and RTL abstractions of the processor, were manually derived from the specification document. The incomplete informal specification document along with manual translation introduces inconsistency and bugs in the validation collaterals, resulting in increased cost and time to validate the processor. We envision a novel metamodeling based microprocessor modeling and validation environment (MMV) to address this problem. MMV provides a language independent modeling environment to the processor at various abstraction levels, a refinement flow to consistently move from one abstraction to lower abstraction and code generators to automatically generate the validation collaterals from the models. As a first step...
Sreekumar V. Kodakara, Deepak Mathaikutty, Ajit Di
Added 30 Nov 2009
Updated 30 Nov 2009
Type Conference
Year 2007
Where VLSID
Authors Sreekumar V. Kodakara, Deepak Mathaikutty, Ajit Dingankar, Sandeep K. Shukla, David J. Lilja
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