Sciweavers

NOCS
2008
IEEE
13 years 11 months ago
A Network of Time-Division Multiplexed Wiring for FPGAs
Rosemary M. Francis, Simon W. Moore, Robert D. Mul...
NOCS
2008
IEEE
13 years 11 months ago
Network Simplicity for Latency Insensitive Cores
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...
Daniel Gebhardt, JunBok You, W. Scott Lee, Kenneth...
NOCS
2008
IEEE
13 years 11 months ago
Adding Slow-Silent Virtual Channels for Low-Power On-Chip Networks
In this paper, we introduce the use of slow-silent virtual channels to reduce the switching power of on-chip networks while keeping the leakage power small. Adding virtual channel...
Hiroki Matsutani, Michihiro Koibuchi, Daihan Wang,...
NOCS
2008
IEEE
13 years 11 months ago
ReNoC: A Network-on-Chip Architecture with Reconfigurable Topology
Mikkel Bystrup Stensgaard, Jens Sparsø
NOCS
2008
IEEE
13 years 11 months ago
Physical Implementation of the DSPIN Network-on-Chip in the FAUST Architecture
Ivan Miro Panades, Fabien Clermidy, Pascal Vivet, ...
NOCS
2008
IEEE
13 years 11 months ago
Reducing the Interconnection Network Cost of Chip Multiprocessors
This paper introduces a cost-effective technique to deal with CMP coherence protocol requirements from the interconnection network point of view. A mechanism is presented to avoid...
Pablo Abad, Valentin Puente, José-Án...
NOCS
2008
IEEE
13 years 11 months ago
Circuit-Switched Coherence
—Circuit-switched networks can significantly lower the communication latency between processor cores, when compared to packet-switched networks, since once circuits are set up, ...
Natalie D. Enright Jerger, Li-Shiuan Peh, Mikko H....