5 search results - page 1 / 1 » Network Simplicity for Latency Insensitive Cores |
NOCS
2008
IEEE
13 years 11 months ago
2008
IEEE
In this paper we examine a latency insensitive network composed of very fast and simple circuits that connects SoC cores that are also latency insensitive, de-synchronized, or asy...
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
Latency-insensitive systems were recently proposed by Carloni et al. as a correct-by-construction methodology for single-clock system-on-a-chip (SoC) design using predesigned IP b...
NOCS
2009
IEEE
13 years 11 months ago
2009
IEEE
We propose Connection then Credits (CTC) as a new end-to-end flow control protocol to handle messagedependent deadlocks in networks-on-chip (NoC) for multicore systems-on-chip. C...
VISUALIZATION
2003
IEEE
13 years 9 months ago
2003
IEEE
We describe an efficient technique for out-of-core management and interactive rendering of planet sized textured terrain surfaces. The technique, called P-Batched Dynamic Adaptiv...
MICRO
2008
IEEE
13 years 11 months ago
2008
IEEE
As chip multiprocessors scale to a greater number of processing cores, on-chip interconnection networks will experience dramatic increases in both bandwidth demand and power dissi...