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2003
IEEE

A New Approach to Test Generation and Test Compaction for Scan Circuits

10 years 9 months ago
A New Approach to Test Generation and Test Compaction for Scan Circuits
We propose a new approach to test generation and test compaction for scan circuits that eliminates the distinction between scan operations and application of primary input vectors. Under this approach, the scan-in, scan-select and scan-out lines are treated as conventional primary inputs or primary outputs of the circuit. As a result, limited scan operations, where scan chains are shifted a number of times smaller than their lengths, are incorporated naturally into the test sequences generated by this approach. This leads to very aggressive compaction, resulting in test sequences with the lowest known test application times for benchmark circuits.
Irith Pomeranz, Sudhakar M. Reddy
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where DATE
Authors Irith Pomeranz, Sudhakar M. Reddy
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