87 search results - page 1 / 18 » A New Approach to Test Generation and Test Compaction for Sc... |
DATE
2003
IEEE
13 years 9 months ago
2003
IEEE
We propose a new approach to test generation and test compaction for scan circuits that eliminates the distinction between scan operations and application of primary input vectors...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
: We present a new, dynamic algorithm for test sequence compaction and test cycle reduction for combinationaland sequential circuits. Several dynamic algorithms for compaction in c...
DATE
2006
IEEE
13 years 10 months ago
2006
IEEE
Transparent-scan was proposed as an approach to test generation and test compaction for scan circuits. Its effectiveness was demonstrated earlier in reducing the test application ...
VLSID
2005
IEEE
14 years 4 months ago
2005
IEEE
Abstract-- We present two-dimensional (space/time) compression techniques that reduce test data volume and test application time for scan testing of intellectual property (IP) core...
DATE
1999
IEEE
13 years 8 months ago
1999
IEEE
Test application time is an important factor in the overall cost of VLSI chip testing. We present a new ATPG approach for generating compact test sequences for sequential circuits...