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TC
2008
11 years 1 months ago
A New Finite-Field Multiplier Using Redundant Representation
A novel serial-in parallel-out finite field multiplier using redundant representation is proposed. It is shown that the proposed architecture has either a significantly lower compl...
Ashkan Hosseinzadeh Namin, Huapeng Wu, Majid Ahmad...
CAL
2007
11 years 1 months ago
Microarchitectures for Managing Chip Revenues under Process Variations
—As transistor feature sizes continue to shrink into the sub-90nm range and beyond, the effects of process variations on critical path delay and chip yields have amplified. A com...
Abhishek Das, Serkan Ozdemir, Gokhan Memik, Joseph...
FPL
2007
Springer
98views Hardware» more  FPL 2007»
11 years 3 months ago
Module Graph Merging and Placement to Reduce Reconfiguration Overheads in Paged FPGA Devices
Reconfiguration time in dynamically-reconfigurable modular systems can severely limit application run-time compared to the critical path delay. In this paper we present a novel ...
Shannon Koh, Oliver Diessel
ASPDAC
2000
ACM
133views Hardware» more  ASPDAC 2000»
11 years 5 months ago
A VLSI implementation of the blowfish encryption/decryption algorithm
We propose an efficient hardware architecture for the Blowfish algorithm [1]. The speed is up to 4 bit/clock, which is 9 times faster than a Pentium. By applying operator-reschedul...
Michael C.-J. Lin, Youn-Long Lin
FPL
2006
Springer
96views Hardware» more  FPL 2006»
11 years 5 months ago
Reducing the Space Complexity of Pipelined Routing Using Modified Range Encoding
Interconnect delays are becoming an increasingly significant part of the critical path delay for circuits implemented in FPGAs. Pipelined interconnects have been proposed to addre...
Allan Carroll, Carl Ebeling
ISCAS
2002
IEEE
92views Hardware» more  ISCAS 2002»
11 years 6 months ago
Low cost floating-point unit design for audio applications
This paper presents a low-cost, single-cycle floating-point unit developed for digital audio processing applications. In the unit, the serial steps of floating-point operations ar...
Sung-Won Lee, In-Cheol Park
IOLTS
2005
IEEE
141views Hardware» more  IOLTS 2005»
11 years 7 months ago
A Novel On-Chip Delay Measurement Hardware for Efficient Speed-Binning
With the aggressive scaling of the CMOS technology parametric variation of the transistor threshold voltage causes significant spread in the circuit delay as well as leakage spect...
Arijit Raychowdhury, Swaroop Ghosh, Kaushik Roy
GLVLSI
2007
IEEE
328views VLSI» more  GLVLSI 2007»
11 years 8 months ago
New timing and routability driven placement algorithms for FPGA synthesis
We present new timing and congestion driven FPGA placement algorithms with minimal runtime overhead. By predicting the post-routing critical edges and estimating congestion accura...
Yue Zhuo, Hao Li, Qiang Zhou, Yici Cai, Xianlong H...
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