Non-uniform Instruction Scheduling

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Non-uniform Instruction Scheduling
Dynamic instruction scheduling logic is one of the most critical and cycle-limiting structures in modern superscalar processors, and it is not easily pipelined without significant losses in performance. However, these performance losses are incurred only due to a small fraction of instructions, which are intolerant to the non-atomic scheduling. We first perform an empirical analysis of the instruction streams to determine which instructions actually require single cycle scheduling. We then propose a Non-Uniform Scheduler – a design that partitions the scheduling logic into two queues, each with dedicated wakeup and selection logic: a small Fast Issue Queue (FIQ) to issue critical instructions in the back-to-back cycles and a large Slow Issue Queue (SIQ) to issue the remaining instructions over two cycles with a one cycle bubble between dependent instructions. Finally, we propose and evaluate several steering mechanisms to effectively distribute instructions between the queues.
Joseph J. Sharkey, Dmitry V. Ponomarev
Added 27 Jun 2010
Updated 27 Jun 2010
Type Conference
Year 2005
Authors Joseph J. Sharkey, Dmitry V. Ponomarev
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