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2001
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Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS Circuits

11 years 7 days ago
Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS Circuits
Development of the process technology for dual threshold (dual Vth ) CMOS circuit has opened up the possibility of using it to reduce static power in low voltage high performance circuits. It has been demonstrated that by using transistors of a low threshold voltage for gates on the critical path, and by using a high threshold voltage for gates in the off-critical path it is possible to significantly reduce leakage power consumption of a circuit without performance degradation. In this paper we have proposed a new algorithm to realize dual threshold CMOS circuits. Our algorithm produces significantly better results for the ISCAS benchmark circuits compared to the reported results.
Nikhil Tripathi, Amit M. Bhosle, Debasis Samanta,
Added 01 Dec 2009
Updated 01 Dec 2009
Type Conference
Year 2001
Where VLSID
Authors Nikhil Tripathi, Amit M. Bhosle, Debasis Samanta, Ajit Pal
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