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ISLPED
1999
ACM

Low power synthesis of dual threshold voltage CMOS VLSI circuits

10 years 4 months ago
Low power synthesis of dual threshold voltage CMOS VLSI circuits
The use of dual threshold voltages can significantly reduce the static power dissipated in CMOS VLSI circuits. With the supply voltage at 1V and threshold voltage as low as 0.2V the subthreshold leakage power of transistors starts dominating the dynamic power. Also, many times a large number of devices spend a long time in a standby mode where the leakage power is the only source of power consumption. We present a near-optimal approach to synthesize low static power CMOS VLSI circuits with two threshold voltages that reduces power consumption compared with a previous approach by upto 29.45%. Also, presented is a technique which finds static power optimal configurations for CMOS VLSI circuits when arbitrary number of threshold voltages are allowed.
Vijay Sundararajan, Keshab K. Parhi
Added 03 Aug 2010
Updated 03 Aug 2010
Type Conference
Year 1999
Where ISLPED
Authors Vijay Sundararajan, Keshab K. Parhi
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