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ISCAS
2011
IEEE

Optimization of area in digit-serial Multiple Constant Multiplications at gate-level

8 years 5 months ago
Optimization of area in digit-serial Multiple Constant Multiplications at gate-level
— The last two decades have seen many efficient algorithms and architectures for the design of low-complexity bit-parallel Multiple Constant Multiplications (MCM) operation, that dominates the complexity of Digital Signal Processing (DSP) systems. On the other hand, digit-serial architectures offer alternative low-complexity designs, since digit-serial operators occupy less area and are independent of the data wordlength. This paper introduces the problem of designing a digit-serial MCM operation with minimal area at gate-level and presents the exact formalization of the area optimization problem as a 0-1 Integer Linear Programming (ILP) problem. Experimental results show the efficiency of the proposed algorithm and digitserial MCM designs in terms of area at gate-level.
Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Pa
Added 21 Aug 2011
Updated 21 Aug 2011
Type Journal
Year 2011
Where ISCAS
Authors Levent Aksoy, Cristiano Lazzari, Eduardo Costa, Paulo F. Flores, José C. Monteiro
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