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ARITH
2003
IEEE

Some Optimizations of Hardware Multiplication by Constant Matrices

10 years 8 months ago
Some Optimizations of Hardware Multiplication by Constant Matrices
This paper presents some improvements on the optimization of hardware multiplication by constant matrices. We focus on the automatic generation of circuits that involve constant matrix multiplication (CMM), i.e. multiplication of a vector by a constant matrix. The proposed method, based on number recoding and dedicated common sub-expression factorization algorithms was implemented in a VHDL generator. The obtained results on several applications have been implemented on FPGAs and compared to previous solutions. Up to 40% area and speed savings are achieved.
Nicolas Boullis, Arnaud Tisserand
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where ARITH
Authors Nicolas Boullis, Arnaud Tisserand
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