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2008
Springer

A Parallel Hardware Architecture for Image Feature Detection

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A Parallel Hardware Architecture for Image Feature Detection
Abstract. This paper presents a real time parallel hardware architecture for image feature detection based on the SIFT (Scale Invariant Feature Transform) algorithm. This architecture receives as input a pixel stream read directly from a CMOS image sensor and produces as output the detected features, where each one is identified by their coordinates, scale and octave. In addition, the proposed hardware also computes the orientation and gradient magnitude for every pixel of one image per octave, which is useful to generate the feature descriptors. This work also presents a suitable parameter set for hardware implementation of the SIFT algorithm and proposes specific hardware optimizations considered fundamental to embed whole system on a single chip, which implements in parallel 18 Gaussian filters, a modified CORDIC (COordinate Rotation DIgital Computer) algorithm version and a considerable number of fixed-point operations, such as those involved in a matrix inversion operation. As a r...
Vanderlei Bonato, Eduardo Marques, George A. Const
Added 12 Oct 2010
Updated 12 Oct 2010
Type Conference
Year 2008
Where ARC
Authors Vanderlei Bonato, Eduardo Marques, George A. Constantinides
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