Parallel placement for field-programmable gate arrays

Placement and routing are the most time-consuming processes in automatically synthesizing and configuring circuits for field-programmable gate arrays (FPGAs). In this paper, we use the negotiation-based paradigm to parallelize placement. Our new FPGA placer, NAP (Negotiated Analytical Placement), uses an analytical technique for coarse placement and the negotiation paradigm for detailed placement. We describe the serial algorithm and report results. We also report findings related to parallelizing NAP under a multicast networking and multi-threaded operating system environment; the parallel placer is tolerant to multicast packet loss as well as out-of-order packet delivery. Our parallel placer exhibits little performance degradation while attaining speedups of 2 using 3 processors. Categories and Subject Descriptors B.7.1 [Integrated Circuits]: Types and Design Styles—Gate arrays; B.7.2 [Integrated Circuits]: Design Aids—Placement and

• Type: Conference
• Year: 2003
• Where: FPGA
• Authors: Pak K. Chan, Martine D. F. Schlag
• Keywords: FPGA 2003, Hardware, Integrated Circuits, Parallel Placer, field-programmable Gate Arrays