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GLVLSI
1996
IEEE

Performance-Driven Interconnect Global Routing

9 years 3 months ago
Performance-Driven Interconnect Global Routing
In this paper, we propose a global routing algorithm for multi-layer building-block layouts. The algorithm is based on successive ripup and rerouting while satisfying edge capacity constraints as well as achieving higher routability and good routing flexibility. The initial solution consists of nets routed independently by the SERT-C algorithm which minimizes the Elmore delay at critical sink of a Steiner tree. Then, all the nets with the most congested edge, i.e., the edge with maximum flow, are ripped up and rerouted by using an iterative hierarchical approach. For each iteration, a window is specified according to the span of the ripped-up nets or an upper bound if the span is too large. Rerouting is done hierarchically within the window by using integer programming to optimize the flow uniformity. The aigorithm terminates when the flow uniformity can not be further improved. The algorithm has been implemented and interfaced with a placement tool. Experiments show that the algorith...
Dongsheng Wang, Ernest S. Kuh
Added 07 Aug 2010
Updated 07 Aug 2010
Type Conference
Year 1996
Where GLVLSI
Authors Dongsheng Wang, Ernest S. Kuh
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