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GLVLSI
1996
IEEE
125views VLSI» more  GLVLSI 1996»
9 years 4 months ago
Performance-Driven Interconnect Global Routing
In this paper, we propose a global routing algorithm for multi-layer building-block layouts. The algorithm is based on successive ripup and rerouting while satisfying edge capacit...
Dongsheng Wang, Ernest S. Kuh
GLVLSI
1996
IEEE
91views VLSI» more  GLVLSI 1996»
9 years 4 months ago
Formal Verification of an ATM Switch Fabric using Multiway Decision Graphs
Sofiène Tahar, Zijian Zhou, Xiaoyu Song, Ed...
GLVLSI
1996
IEEE
128views VLSI» more  GLVLSI 1996»
9 years 4 months ago
Delay Hazards in Complex Gate Based Speed Independent VLSI Circuits
Nozar Tabrizi, Michael J. Liebelt, Kamran Eshraghi...
GLVLSI
1996
IEEE
126views VLSI» more  GLVLSI 1996»
9 years 4 months ago
An Accurate Interconnection Length Estimation for Computer Logic
Important layout properties of electronic designs include space requirements and interconnection lengths. A reliable interconnection length estimation is essential for improving p...
Dirk Stroobandt, Herwig Van Marck, Jan Van Campenh...
GLVLSI
1996
IEEE
88views VLSI» more  GLVLSI 1996»
9 years 4 months ago
A High Speed VLSI Architecture for Scaleable ATM Switches
Paul Shipley, Sherif Sayed, Magdy A. Bayoumi
GLVLSI
1996
IEEE
102views VLSI» more  GLVLSI 1996»
9 years 4 months ago
FPGA-based high performance page layout segmentation
Nalini K. Ratha, Anil K. Jain, Diane T. Rover
GLVLSI
1996
IEEE
103views VLSI» more  GLVLSI 1996»
9 years 4 months ago
A Parametrical Architecture for Reed-Solomon Decoders
Mariana-Eugenia Petre, Guido Masera
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