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EURODAC
1995
IEEE

Performance-oriented placement and routing for field-programmable gate arrays

8 years 9 months ago
Performance-oriented placement and routing for field-programmable gate arrays
This paper presents a performance-oriented placement and routing tool for field-programmable gate arrays. Using recursive geometric partitioning for simultaneous placement and global routing, and a graphbased strategy for detailed routing, our tool optimizes source-sink pathlengths, channel width and total wirelength. Our results compare favorably with other FPGA layout tools, as measured by the maximum channel width required to place and route a number of industrial benchmarks. -',;?:<; .-' I - ' I ',/ Switch Block
Michael J. Alexander, James P. Cohoon, Joseph L. G
Added 26 Aug 2010
Updated 26 Aug 2010
Type Conference
Year 1995
Where EURODAC
Authors Michael J. Alexander, James P. Cohoon, Joseph L. Ganley, Gabriel Robins
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