GLVLSI
2007
IEEE
13 years 4 months ago
2007
IEEE
Given a set of placed blocks, we present an algorithm that minimally spaces the blocks to ensure routability under several assumptions. By performing a binary search on total widt...
EURODAC
1995
IEEE
13 years 8 months ago
1995
IEEE
This paper presents a performance-oriented placement and routing tool for field-programmable gate arrays. Using recursive geometric partitioning for simultaneous placement and glo...
FPL
2006
Springer
13 years 8 months ago
2006
Springer
We introduce a new congestion driven placement algorithm for FPGAs in which the overlappingeffect of boundingboxes is taken into consideration. Experimental results show that comp...
DAC
2005
ACM
14 years 5 months ago
2005
ACM
In this paper we present a system level technique for mapping large, multiple-IP-block designs to channel-width constrained FPGAs. Most FPGA clustering tools [2, 3, 11] aim to red...