A process algebra interpretation of a verification oriented overlanguage of VHDL

13 years 8 months ago

The VOVHDL language was defined as a verification oriented VHDL

Catherine Bayol, Bernard Soulas, Dominique Borrion

EURODAC 1994 | EVAL CCSbased Verification | Formal Semantic Model | VHDL | VHDL Simulable Specification |

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Added	08 Aug 2010
Updated	08 Aug 2010
Type	Conference
Year	1994
Where	EURODAC
Authors	Catherine Bayol, Bernard Soulas, Dominique Borrione, Fulvio Corno, Paolo Prinetto

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