Side-channel resistant system-level design flow for public-key cryptography

In this paper, we propose a new design methodology to assess the risk for side-channel attacks, more specifically timing analysis and simple power analysis, at an early design stage. This method is illustrated with the design of an elliptic curve cryptographic processor. It also allows to evaluate the quality of countermeasures against these attacks by evaluating hamming distances for each signal and each register in a partial functional domain (e.g. datapath or controller). Thus a first order side-channel-resistant design can be obtained with system-level design in which the simulation can run faster than conventional HDL simulations. Categories and Subject Descriptors: B.7.2 Design Aids: Verification, C.3 Special-purpose and application-based design: Smartcards. General Terms: Design, Security, Verification.

• Type: Conference
• Year: 2007
• Where: GLVLSI
• Authors: Kazuo Sakiyama, Elke De Mulder, Bart Preneel, Ingrid Verbauwhede
• Keywords: Design, Early Design Stage, GLVLSI 2007, Order Side-channel-resistant Design, VLSI