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DATE
2009
IEEE

Single ended 6T SRAM with isolated read-port for low-power embedded systems

10 years 5 months ago
Single ended 6T SRAM with isolated read-port for low-power embedded systems
Abstract— This paper presents a six-transistor (6T) singleended static random access memory (SE-SRAM) bitcell with an isolated read-port, suitable for low-Î and low-power embedded applications. The proposed bitcell has a better static noise margin (SNM) and write-ability compared to a standard 6T bitcell and equivalent to an 8T bitcell [1]. An Kbit SRAM module with the proposed and standard 6T bitcells is simulated, including full blown parasitics using BPTM, nm CMOS technology node to evaluate and compare different performance parameters. The active power dissipation in the proposed 6T design is ¾ ± and ¾ ± less, compared to standard 6T and 8T SRAM modules respectively.
Jawar Singh, Dhiraj K. Pradhan, Simon Hollis, Sara
Added 20 May 2010
Updated 20 May 2010
Type Conference
Year 2009
Where DATE
Authors Jawar Singh, Dhiraj K. Pradhan, Simon Hollis, Saraju P. Mohanty, Jimson Mathew
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