Sciweavers

Share
FPGA
2009
ACM

SmartOpt: an industrial strength framework for logic synthesis

9 years 1 months ago
SmartOpt: an industrial strength framework for logic synthesis
In recent years, the maximum logic capacity of each successive FPGA family has been increasing by more than 50%, which motivates scalable solutions. Meanwhile, academic research in logic synthesis has been fruitful, but these advances have been demonstrated on academic architectures and benchmark designs which are not representative of modern industrial FPGAs. This paper presents a framework (SmartOpt) for mapping complex FPGA architectures to a simple netlist model, which can be supported by academic tools. SmartOpt was applied to leverage the algorithms implemented in the ABC package and to study their relative contributions. This work is integrated into the Xilinx ISE
Stephen Jang, Dennis Wu, Mark Jarvin, Billy Chan,
Added 19 May 2010
Updated 19 May 2010
Type Conference
Year 2009
Where FPGA
Authors Stephen Jang, Dennis Wu, Mark Jarvin, Billy Chan, Kevin Chung, Alan Mishchenko, Robert K. Brayton
Comments (0)
books