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DATE
2005
IEEE

SOC Testing Methodology and Practice

10 years 4 months ago
SOC Testing Methodology and Practice
Abstract—On a commercial digital still camera (DSC) controller chip we practice a novel SOC test integration platform, solving real problems in test scheduling, test IO reduction, timing of functional test, scan IO sharing, embedded memory built-in self-test (BIST), etc. The chip has been fabricated and tested successfully by our approach. Test results justify that short test integration cost, short test time, and small area overhead can be achieved. To support SOC testing, a memory BIST compiler and an SOC testing integration system have been developed.
Cheng-Wen Wu
Added 24 Jun 2010
Updated 24 Jun 2010
Type Conference
Year 2005
Where DATE
Authors Cheng-Wen Wu
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