A Source-Level Dynamic Analysis Methodology and Tool for High-Level Synthesis

This paper presents a novel source-level dynamic analysis methodology and tool for High-Level Synthesis (HLS). It not only for the first time enables HLS to offer source-level design debugging on the ‘synthesized’ RTL designs, but also allows the designer to analyze their dynamic characteristics, such as resource utilization, power consumption, etc., at the algorithmic (source) level. This technology has been proven in the industry as the critical element for successfully designing a microcontroller with 300+ instructions with Matisse, an interactive HLS system. Additionally, we demonstrate the use of this technology for architectural power optimization.

• Type: Conference
• Year: 1997
• Where: ISSS
• Authors: Chih-Tung Chen, Kayhan Küçükçakar
• Keywords: Hardware, Interactive Hls System, ISSS 1997, Source-level Dynamic Analysis, first Time Enables