10 search results - page 1 / 2 » A Source-Level Dynamic Analysis Methodology and Tool for Hig... |
ISSS
1997
IEEE
13 years 9 months ago
1997
IEEE
This paper presents a novel source-level dynamic analysis methodology and tool for High-Level Synthesis (HLS). It not only for the first time enables HLS to offer source-level de...
DATE
2004
IEEE
13 years 8 months ago
2004
IEEE
In this paper we analyse some methodological concerns that have to be faced in a design flow which contains automatic synthesis phases from high-level, system descriptions. In par...
TRETS
2010
13 years 3 months ago
2010
s, and abstractions, typically enabling faster development times than with traditional Hardware ion Languages (HDLs). However, programming at a higher level of abstraction is typic...
DSD
2010
IEEE
13 years 2 months ago
2010
IEEE
Reconfigurable FPGA based Systems-on-Chip (SoC) architectures are increasingly becoming the preferred solution for implementing modern embedded systems, due to their flexible natur...
DATE
1999
IEEE
1999
IEEE
Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs
13 years 9 months ago
This paper reports a formal methodology for verifying a broad class of synthesized register-transfer-level (RTL) designs by accommodating various register allocation/optimization ...