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ISQED
2003
IEEE

Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets

10 years 7 days ago
Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets
An algorithm for mapping core terminals to System-On-a-Chip (SOC) I/O pins and scheduling tests in order to achieve costefficient concurrent test for core-based designs is presented in this paper. In this work "static" pin mapping and test scheduling for concurrent testing are studied for the case of multiple test sets for each core. The problem is formulated as a constrained two-dimensional bin-packing problem. A heuristic algorithm is then proposed to determine a solution. The objectives driving this solution are geared towards reducing the total test application time of SOC and satisfying the test constraints such as limited number of SOC pins and maximum peak power dissipation specified by core integrators. Experimental results demonstrate the effectiveness of the proposed method.
Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanja
Added 04 Jul 2010
Updated 04 Jul 2010
Type Conference
Year 2003
Where ISQED
Authors Yu Huang, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee, Sudhakar M. Reddy
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