4 search results - page 1 / 1 » Static Pin Mapping and SOC Test Scheduling for Cores with Mu... |
ISQED
2003
IEEE
13 years 9 months ago
2003
IEEE
An algorithm for mapping core terminals to System-On-a-Chip (SOC) I/O pins and scheduling tests in order to achieve costefficient concurrent test for core-based designs is present...
VLSID
2002
IEEE
14 years 5 months ago
2002
IEEE
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
GLVLSI
2002
IEEE
13 years 9 months ago
2002
IEEE
We present a novel test scheduling algorithm for embedded corebased SoC’s. Given a system integrated with a set of cores and a set of test resources, we select a test for each c...
CODES
2010
IEEE
13 years 1 months ago
2010
IEEE
This paper presents an approach to system-level optimization of error detection implementation in the context of fault-tolerant realtime distributed embedded systems used for safe...