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ICCD
2004
IEEE

Toward an Integrated Design Methodology for Fault-Tolerant, Multiple Clock/Voltage Integrated Systems

12 years 11 months ago
Toward an Integrated Design Methodology for Fault-Tolerant, Multiple Clock/Voltage Integrated Systems
Abstract - This paper describes a communicationcentric design methodology that addresses the fundamental challenges induced by the emergence of truly heterogeneous Systems-on-Chip (SoCs). For such systems, the globally asynchronous design paradigm seems to be the most promising (if not the only) solution for providing an underlying substrate for cost-effective and power efficient on-chip communication among diverse, mixed technology IPs. Additional challenges are related to reliability and error resilience of on-chip communication architectures. The proposed on-chip communication methodology targets all levels of ion, from circuit, to microarchitecture and system-level by seamlessly integrating solutions for robust and efficient globally asynchronous communication among diverse IPs.
Radu Marculescu, Diana Marculescu, Larry T. Pilegg
Added 16 Mar 2010
Updated 16 Mar 2010
Type Conference
Year 2004
Where ICCD
Authors Radu Marculescu, Diana Marculescu, Larry T. Pileggi
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