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2002
IEEE

Transistor Flaring in Deep Submicron-Design Considerations

10 years 11 months ago
Transistor Flaring in Deep Submicron-Design Considerations
Abstract - The deep sub-micron regime has broughtup several manufacturing issues which impact circuit-performance and design. One such issue is flaring of transistors which causes the channel length to vary along the transistor width. It seriously impacts self-alignment of the CMOS process, causes transistor-matching issues, and makes accurate transistor modeling difficult. It can have significant adverse yield impact. In this paper, the effect, its consequences, and different solutions are examined. A methodology for modeling the effect of flaring on transistor performance is introduced. Different solutions for high density and high performance designs are proposed.
Vipul Singhal, C. B. Keshav, K. G. Surnanth, P. R.
Added 01 Dec 2009
Updated 01 Dec 2009
Type Conference
Year 2002
Where VLSID
Authors Vipul Singhal, C. B. Keshav, K. G. Surnanth, P. R. Suresh
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