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ISCAS
2005
IEEE

Transition time bounded low-power clock tree construction

10 years 5 months ago
Transition time bounded low-power clock tree construction
— Recently power becomes a significant issue in clock network design for high-performance ICs because the clock network consumes a large portion of the total power in the whole system. Also, clock signal is the signal with the highest frequency in the whole system, which makes the transition time bound of the clock signal extremely tight. Hence, it is necessary to have transition time bounds to construct low-power clock trees in high performance systems. In this paper, we formulate the transition time bounded low-power clock tree construction problem. Buffer insertion, buffer sizing and wire sizing are employed to construct the low-power clock tree under a given transition time bound. We propose a top-down dynamic programming algorithm to solve the problem. Experimental results show that the transition time bound has a significant effect on power consumption. Therefore, we need to consider the trade-off between transition time and power consumption in clock tree design. In addition, ...
Min Pan, Chris C. N. Chu, J. Morris Chang
Added 25 Jun 2010
Updated 25 Jun 2010
Type Conference
Year 2005
Where ISCAS
Authors Min Pan, Chris C. N. Chu, J. Morris Chang
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