Unified P4 (power-performance-process-parasitic) fast optimization of a Nano-CMOS VCO

In this paper, we present the design of a P4 (Power-PerformanceProcess-Parasitic) aware voltage controlled oscillator (VCO) at nanoCMOS technologies. Through simulations, we have shown that parasitics and process have a drastic effect on the performance (center frequency) of the VCO. For process variation analysis, we propose a methodology called Design of Experiments-Monte Carlo (DOE-MC), which offers up to 6.25x time savings over a traditional Monte Carlo (TMC) method. A performance optimization of the VCO along with dual-oxide power minimization technique has been carried out in the presence of worst case process. The end product of the proposed methodology is a process aware, performance optimized, dual oxide VCO physical design. We have achieved 25% power (including leakage) minimization with only 1% degradation in center frequency compared to target frequency, in the presence of worst-case process and parasitics. The dualoxide physical design of the VCO is carried out at 90nm. T...

• Type: Conference
• Year: 2009
• Where: GLVLSI
• Authors: Dhruva Ghai, Saraju P. Mohanty, Elias Kougianos
• Keywords: Aware Design, Center Frequency, GLVLSI 2009, Process Variation, VLSI