The Validity of Retiming Sequential Circuits

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The Validity of Retiming Sequential Circuits
Retiming has been proposed as an optimizationstep forsequential circuits represented at the net-list level. Retiming moves the latches across the logic gates and in doing so changes the number of latches and the longest path delay between the latches. In this paper we show by example that retiming a design may lead to differing simulation results when the retimed design replaces the original design. We also show, by example, that retiming may not preserve the testability of a sequential test sequence for a given stuck-at fault as measured by a simulator. We identifythe cause of the problem as forwardretiming moves across multiple-fanout points in the circuit. The primary contribution of this paper is to show that, while an accurate logic simulation may distinguish the retimed circuit fromthe originalcircuit, a conservative three-valued simulator cannot do so. Hence, retiming is a safe operation when used in a design methodology based on conservative three-valued simulation starting ea...
Vigyan Singhal, Carl Pixley, Richard L. Rudell, Ro
Added 26 Aug 2010
Updated 26 Aug 2010
Type Conference
Year 1995
Where DAC
Authors Vigyan Singhal, Carl Pixley, Richard L. Rudell, Robert K. Brayton
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