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ASPDAC
2006
ACM

Worst case execution time analysis for synthesized hardware

12 years 5 months ago
Worst case execution time analysis for synthesized hardware
- We propose a hardware performance estimation flow for fast design space exploration, based on worst-case execution time analysis algorithms for software analysis. Test cases on some real-world applications show that our flow provides a tight upper bound of the execution time, and many useful hints to the designer.
Jun-hee Yoo, Xingguang Feng, Kiyoung Choi, Eui-You
Added 13 Jun 2010
Updated 13 Jun 2010
Type Conference
Year 2006
Where ASPDAC
Authors Jun-hee Yoo, Xingguang Feng, Kiyoung Choi, Eui-Young Chung, Kyu-Myung Choi
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